Use of finite state machines and algorithmic state machines in hardware description languages

Abstract

In this thesis a methodology for the development of hardware description programs is proposed, applying as a didactic strategy the use of Finite State Machines and Algorithmic State Machines as an approach in the analysis to the problems posed and trying to establish a phase scheme for problem solving as it was done in the design of programs in the basic programming courses by establishing programming methodologies that allowed a prior analysis of the problem and then its design and editing. And so, give support to Computer Architecture students of the third semester of the Systems Engineering degree who use the hardware description languages as transversal knowledge of the course, hence a self-learning of the same is applied

First, the use of finite state machines in the design of sequential circuits is addressed and then a Algorithmic state machine to be able to arrive in a more simple and didactic way to the programming in VHDL.

By means of hardware description languages, it is possible to simplify circuits and the use of analysis tools such as FMS and ASM allows us to develop sequential circuits in their minimum expression, fulfilling the tasks entrusted to their development.